Approx-IMC: A general-purpose approximate digital in-memory computing framework based on STT-MRAM

被引:1
|
作者
Hajisadeghi, Amir M. [1 ]
Momtazpour, Mahmoud [1 ]
Zarandi, Hamid R. [1 ]
机构
[1] Tehran Polytech, Dept Comp Engn, Amirkabir Univ Technol, Tehran, Iran
关键词
In-Memory Computing (IMC); Non-Volatile Memory (NVM); Data-intensive application; Approximate computing; Spin-transfer-torque MRAM (STT-MRAM);
D O I
10.1016/j.future.2024.05.053
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
In -memory computing (IMC) empowers von Neumann -based computing systems to meet the performance and energy requirements of emerging data -intensive applications by offloading some computations to memory. Fortunately, many data -intensive applications that can benefit from IMC, such as image processing and neural networks, can tolerate minor accuracy loss to some extent. In this paper, we exploit this potential by using approximate computing to make a good tradeoff between performance, energy, and accuracy of data -intensive approximable applications in memory. In this regard, we present a general-purpose STT-MRAMbased digital IMC framework called Approx-IMC that, with the help of approximate computing, improves the performance and energy consumption of (multi -bit) arithmetic operations as building blocks used in data -intensive approximable applications. Approx-IMC effectively implements the given building blocks in memory in accurate and approximate fashions. To do this, first, efficient logic selection and logic synthesis are done for each building block regarding the reliability considerations of the supported in -memory logics. Next, to minimize the building blocks' execution time, the in -memory scheduling and mapping task is formulated as an integer linear programming (ILP) optimization problem. After that, the building blocks are introduced to CPU ISA as extended instructions to support the Approx-IMC blocks. Moreover, Approx-IMC memory architecture and system integration aspects have been addressed. Finally, to evaluate the framework's efficiency, the main arithmetic building blocks in most applications, including full adder, adder, and multiplier, have been implemented, and circuit-, architecture-, and application -level analyses have been conducted. The results over real -world applications reveal that by following our proposed framework, significant speedup and energy improvement can be achieved compared to CPU and a well-known in -memory computing mechanism. Furthermore, reliability evaluations show high process variation robustness and lifetime improvement.
引用
收藏
页码:40 / 53
页数:14
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