共 37 条
- [1] Mittal S., A survey of techniques for architecting and managing asymmetric multicore processors, ACM Computing Surveys, 48, 3, pp. 1-38, (2016)
- [2] Kumar R, Farkas KI, Jouppi NP, Et al., Single-ISA heterogeneous multi-core architectures: The potential for processor power reduction, Proc. of the 36th Annual IEEE/ACM Int'l Symp. on Microarchitecture, pp. 81-92, (2003)
- [3] Kumar R, Tullsen DM, Ranganathan P, Et al., Single-ISA heterogeneous multi-core architectures for multithreaded workload performance, Proc. of the ACM SIGARCH Computer Architecture News, 64, (2004)
- [4] Greenhalgh P., Big.LITTLE processing with ARM CortexTM-A15 & Cortex-A7, Proc. of the ARM, pp. 1-8, (2011)
- [5] Shiu E, Prakash S., System challenges and hardware requirements for future consumer devices: From wearable to ChromeBooks and devices in-between, Proc. of the IEEE 2015 Symp. on VISI Technology, pp. 1-5, (2015)
- [6] Lu F, Cui HM, Huo W, Et al., Survey of scheduling policies for co-run degradation, Journal of Computer Research and Development, 51, 1, pp. 17-30, (2014)
- [7] Koufaty D, Reddy D, Hahn S., Bias scheduling in heterogeneous multi-core architectures, Proc. of the 5th European Conf. on Computer Systems, pp. 125-138, (2010)
- [8] Srinivasan S, Kurella N, Koren I, Et al., Exploring heterogeneity within a core for improved power efficiency, IEEE Trans. on Parallel and Distributed Systems, 27, 4, pp. 1057-1069, (2016)
- [9] McKenny P., A big.LITTLE scheduler update, (2012)
- [10] Tseng PH, Hsiu PC, Pan CC, Et al., User-Centric energy-efficient scheduling on multi-core mobile devices, Proc. of the 51st Annual Design Automation Conf. (DAC 2014), pp. 1-6, (2014)