Input bias current reduction technique for operational amplifier in a standard CMOS technology

This paper presents input bias current (Ibias) reduction technique for high impedance CMOS op-amps with the proposed current compensation circuit to deal with the leakage current caused by Electro-Static Discharge (ESD) protection circuit of the IC. High input impedance CMOS op-amps are widely used for the application of high precision sensors with quite small input current. However, the leakage current of ESD protection circuit for op-amp causes a non-ideality error of the Ibias. Especially, the ESD leakage current increases drastically at the high temperature environment, and hence the Ibias of CMOS op-amp also increased significantly. An ESD leakage current compensation circuit is introduced to reduce the Ibias of CMOS op-amp. The prototype amplifier with the proposed current compensation circuit is designed and fabricated in standard 0.7 µm CMOS technology. Measurement results show that the Ibias is reduced to a 100 pA or less from a typical 2.3 nA at 150°C. © 2020 The Institute of Electrical Engineers of Japan.