AN ANALYTIC MODEL OF HOLDING VOLTAGE FOR LATCH-UP IN EPITAXIAL CMOS

被引：24
|
作者：
SEITCHIK, JA
CHATTERJEE, A
YANG, P
机构：
来源：
IEEE ELECTRON DEVICE LETTERS | 1987年 / 8卷 / 04期
关键词：
D O I：
10.1109/EDL.1987.26586
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：157 / 159
页数：3
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