VHDL, VERILOG-HDL, AND UDL I-FEATURE DESCRIPTION AND ANALYSIS

被引：0
|
作者：
SANKARSHANAN, PN
KOBAYASHI, H
KUKKAL, P
KANBARA, H
机构：
来源：
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS | 1993年 / E76D卷 / 09期
关键词：
HARDWARE DESCRIPTION LANGUAGES; MICROPROCESSOR DESIGN; VLSI DESIGN;
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents a description and an analysis of three ''standard'' hardware description languages (HDLs): Very High Speed Integrated Circuit HDL (VHDL), Verilog-HDL, and Unified Design Language for Integrated Circuits (UDL/I). Kyoto University Education Chip (KUE-Chip) is used as a design benchmark to compare the features and syntax of VHDL, Verilog-HDL, and UDL/I.
引用
收藏
页码：1055 / 1065
页数：11
相关论文
共 3 条
  • [1] Integrating of Verilog-HDL and VHDL languages in the SMASH™ mixed-signal multi-level simulator
    Sauge, P
    Thuau, G
    1998 INTERNATIONAL VERILOG HDL CONFERENCE AND VHDL INTERNATIONAL USERS FORUM, PROCEEDINGS, 1998, : 2 - 6
  • [2] VHDL - FEATURE DESCRIPTION AND ANALYSIS
    AYLOR, JH
    WAXMAN, R
    SCARRATT, C
    IEEE DESIGN & TEST OF COMPUTERS, 1986, 3 (02): : 17 - 27
  • [3] A D-AND-T ROUNDTABLE - BEHAVIORAL DESCRIPTION LANGUAGES .2. VHDL VS UDL/I
    WERNER, J
    BAKALAR, K
    COELHO, D
    HOSHINO, T
    KARATSU, O
    MALEY, J
    WAXMAN, R
    IEEE DESIGN & TEST OF COMPUTERS, 1990, 7 (02): : 64 - 68
1