ALU DESIGN AND PROCESSOR BRANCH ARCHITECTURE

This paper examines the role of the ALU within the context of high-performance processor design. In particular, the functional requirements of various processor branch architectures are evaluated and related to ALU design. The paper demonstrates that the traditional condition code branch mechanism is unsuitable for high-performance, multiple-instruction-issue processor implementations. First, the use of condition codes hinders code motion and therefore inhibits instruction scheduling. Second, the use of condition codes prevents the early resolution of branch conditions and therefore either increases the processor cycle time or the number of branch delay slots. Various alternative branch mechanisms are examined which remove the first restriction. Two of the branch architectures considered are also shown to remove the second problem. In both architectures the crucial factor is that only a single branch condition needs to be evaluated for each branch. Outline designs of a Relational Unit and an ALU which meet the requirements of the two high-performance branch architectures are also presented and compared with traditional ALU and comparator designs.