FORMAL METHODS AND VLSI ENGINEERING PRACTICE

被引：0
|
作者：
STAVRIDOU, V
机构：
[1] Univ of London, Egham Surrey
来源：
COMPUTER JOURNAL | 1994年 / 37卷 / 02期
关键词：
D O I：
10.1093/comjnl/37.2.96
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper surveys the state of the art in the use of formal verification for hardware design and discusses the transfer of such methods to industrial practice. We examine the characteristics of the VLSI engineering process and propose a set of criteria for evaluating the applicability of various formal approaches to the design of digital systems. We also discuss some topics for future research to enable effective technology transfer of formal methods to VLSI engineering practice.
引用
收藏
页码：96 / 113
页数：18
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