ONE-BIT ADDER DESIGN BASED ON REED-MULLER EXPANSIONS

It has been claimed for some time that the Reed-Muller technique can yield a simpler arithmetic circuit if it is employed in the design procedure. In fact, no practical application in this field can be found in the open literature. This paper attempts to demonstrate a practical one-bit adder design that is based on the Reed-Muller expansion. Although the one-bit adder is simple, no method can always guarantee to obtain both a time and area optimal circuit. In this paper, a procedure to design both a time and area optimal one-bit adder in static CMOS circuits is presented. Some issues are also addressed for practical logic circuit design.