A SUBMICROMETER MOS-TRANSISTOR IV MODEL FOR CIRCUIT SIMULATION

This paper describes a submicrometer MOSFET model that is used as a circuit simulator. The object is to realize a simple I-V model that receives good agreement with the experimental result including its geometrical effects. To achieve this, we have developed 1) a novel semi-empirical formula for channel conductance degradation by gate electric field and 2) a compact channel-length modulation model for short channel MOSFET operation in the saturation region. Geometrical effects on the MOSFET model parameters are also studied, focusing on the channel conductance and threshold voltage. Based on experimental verification with CMOS devices fabricated by 0.5-1.3-mu-m technologies, it is concluded that the proposed I-V model and geometrical formulas of the model parameters coincide with the experimental data with the maximum rms error of 1%.