Design and Modelling of 6T FinFET SRAM in 18nm

被引:0
|
作者
Vijayalakshmi, V. [1 ]
Naik, B. Mohan Kumar [1 ]
机构
[1] VTU, New Horizon Coll Engn, Dept ECE, Bangalore, Karnataka, India
关键词
SRAM; FinFET; Average Power;
D O I
暂无
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
In this work FinFET based of 6T SRAM were designed and characterized these cells in terms of temperature and average power. This SRAMs were designed & stimulated in Cadence using 18nm FinFET technology.
引用
收藏
页码:208 / 211
页数:4
相关论文
共 50 条
  • [31] Characterization of various FinFET based 6T SRAM cell configurations in light of radiation effect
    Limachia, Mitesh
    Kothari, Nikhil
    SADHANA-ACADEMY PROCEEDINGS IN ENGINEERING SCIENCES, 2020, 45 (01):
  • [32] Design and Analysis of 6T, 8T and 9T Decanano SRAM Cell at 45 nm Technology
    Randhawa, Yogeshwar Singh
    Sharma, Sanjay
    JOURNAL OF COMPUTATIONAL AND THEORETICAL NANOSCIENCE, 2012, 9 (10) : 1686 - 1692
  • [33] Performance Evaluation of FinFET Based 6T and Gated Ground 7T SRAM Cell's
    Kushwah, Ravindra Singh
    Khandelwal, Saurabh
    Akashe, Shyam
    JOURNAL OF ACTIVE AND PASSIVE ELECTRONIC DEVICES, 2014, 9 (01): : 1 - 11
  • [34] Design and Implementation of 6T SRAM Circuitry System using FINFETs
    Vemula, Panduranga
    Dhar, Rudra Sankar
    PRZEGLAD ELEKTROTECHNICZNY, 2024, 100 (07): : 84 - 88
  • [35] Process Variation's Effect on Various Threshold Voltage Assignments in 6T SRAM Designs Using 12nm FinFET Technology
    Irin, Umme Hani
    Barua, Sajib
    Azmir, Md Minhajul
    Hassan, Tasnuva
    Mohammed, Dewan
    2023 IEEE 13TH ANNUAL COMPUTING AND COMMUNICATION WORKSHOP AND CONFERENCE, CCWC, 2023, : 928 - 932
  • [36] Tunneling Transistor based 6T SRAM Bitcell Circuit Design in Sub-10nm Domain
    Hossain, Nahid
    Iqbal, Arif
    Shishupal, Hemanshu
    Chowdhury, Masud H.
    2017 IEEE 60TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2017, : 1485 - 1488
  • [37] Design of a Stable Read-Decoupled 6T SRAM Cell at 16-nm Technology Node
    Anand, Nitin
    Sinha, Anubhav
    Roy, Chandramauleshwar
    Islam, Aminul
    2015 IEEE INTERNATIONAL CONFERENCE ON COMPUTATIONAL INTELLIGENCE AND COMMUNICATION TECHNOLOGY CICT 2015, 2015, : 524 - 528
  • [38] Design and analysis of high-speed 8-bit ALU using 18nm FinFET technology
    Shylashree, N.
    Venkatesh, B.
    Saurab, T. M.
    Srinivasan, Tarun
    Nath, Vijay
    MICROSYSTEM TECHNOLOGIES-MICRO-AND NANOSYSTEMS-INFORMATION STORAGE AND PROCESSING SYSTEMS, 2019, 25 (06): : 2349 - 2359
  • [39] Comparison of 6T and 8T SRAM Cell with Parameters at 45 nm Technology
    Sharma, Joshika
    Khandelwal, Saurabh
    Akashe, Shyam
    ADVANCES IN OPTICAL SCIENCE AND ENGINEERING, 2015, 166 : 263 - 267
  • [40] Design Method for 6T CNFET Misalignment Immune SRAM Circuit
    Wang, Wei
    Yu, Zhiyuan
    He, Peiwen
    Choi, Ken
    Lee, Hojoon
    2011 IEEE 54TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2011,