Through silicon vias filled with planarized carbon nanotube bundles

被引：46

作者：

Wang, Teng ^{[1
,2
]}

Jeppson, Kjell ^{[1
]}

Olofsson, Niklas ^{[3
]}

Campbell, Eleanor E. B. ^{[4
,5
]}

Liu, Johan ^{[1
,6
,7
]}

机构：

[1] Chalmers Univ Technol, Dept Microtechnol & Nanosci, SE-41296 Gothenburg, Sweden

[2] SHT Smart High Tech AB, SE-42834 Kallered, Sweden

[3] Univ Gothenburg, Dept Phys, SE-41296 Gothenburg, Sweden

[4] Univ Edinburgh, Sch Chem, Edinburgh EH9 3JJ, Midlothian, Scotland

[5] Konkuk Univ, Dept Phys, Seoul 143701, South Korea

[6] Shanghai Univ, Sch Mech Engn & Automat, Key Lab New Displays & Syst Applicat, Shanghai 200072, Peoples R China

[7] Shanghai Univ, Sch Mech Engn & Automat, SMIT Ctr, Shanghai 200072, Peoples R China

来源：

NANOTECHNOLOGY | 2009年 / 20卷 / 48期

基金：

瑞典研究理事会; 美国国家科学基金会;

关键词：

THROUGH-SILICON; INTERCONNECTS; GROWTH;

D O I：

10.1088/0957-4484/20/48/485203

中图分类号：

TB3 [工程材料学];

学科分类号：

0805 ; 080502 ;

摘要：

The feasibility of using carbon nanotube (CNT) bundles as the fillers of through silicon vias (TSVs) has been demonstrated. CNT bundles are synthesized directly inside TSVs by thermal chemical vapor deposition (TCVD). The growth of CNTs in vias is found to be highly dependent on the geometric dimensions and arrangement patterns of the vias at atmospheric pressure. The CNT-Si structure is planarized by a combined lapping and polishing process to achieve both a high removal rate and a fine surface finish. Electrical tests of the CNT TSVs have been performed and their electrical resistance was found to be in the few hundred ohms range. The reasons for the high electrical resistance have been discussed and possible methods to decrease the electrical resistance have been proposed.

引用

页数：6

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