A top-down methodology for microprocessor validation

被引：8
|
作者：
Mishra, P
Dutt, N
Krishnamurthy, N
Abadir, MS
机构：
[1] Univ Calif Irvine, Ctr Embedded Comp Syst, Irvine, CA 92697 USA
[2] Univ Calif Irvine, Sch Informat & Comp Sci, Irvine, CA 92697 USA
[3] Motorola Inc, PowerPC Design Ctr, High Performance Tools & Methodol Grp, Austin, TX USA
来源：
IEEE DESIGN & TEST OF COMPUTERS | 2004年 / 21卷 / 02期
关键词：
D O I：
10.1109/MDT.2004.1277905
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Equivalence checking is a formal technique that is popular in industry today. Typically, this technique involves comparing the implementation to a set of Boolean equations or comparing an optimized circuit to the original circuit. Symbolic simulation is an efficient technique that bridges the gap between traditional simulation and full-fledged formal verification. This paper presents a top-down methodology for validation of microprocessors using a combination of symbolic simulation and equivalence checking.
引用
收藏
页码：122 / 131
页数：10
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